Re: [PATCH v6 4/5] shared memory: Define PCI capability

From
Cornelia Huck <>
Date
2019-07-12T09:01:48+00:00
ID
Thread
Re: [PATCH v6 4/5] shared memory: Define PCI capability
On Wed, 10 Jul 2019 19:32:11 +0100
"Dr. David Alan Gilbert (git)" <> wrote:

> From: "Dr. David Alan Gilbert" <>
> 
> Define the PCI capability used for enumerating shared memory regions.
> 
> Signed-off-by: Dr. David Alan Gilbert <>
> ---
>  content.tex | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 

(...)

> +\devicenormative{\paragraph}{Device-specific configuration}{Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / Shared memory capability}

Sorry about not noticing that before, but doesn't that need to be
referenced in the conformance section somewhere?

> +
> +The region defined by the combination of the \field {cap.offset},
> +\field {cap.offset_hi}, and \field {cap.length}, \field
> +{cap.length_hi} fields MUST be contained within the declared bar.
> +
> +The \field{cap.id} MUST be unique for any one device instance.
> +
>  \subsubsection{PCI configuration access capability}\label{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / PCI configuration access capability}
>  
>  The VIRTIO_PCI_CAP_PCI_CFG capability

Otherwise, looks good.