Feedback on ISR status register: It would be helpful if this section provided the meaning of each bit in the register. ISR use is scattered all around the place. Add a section describing the format and semantics.
Cc: Arun Subbarao <> Signed-off-by: Michael S. Tsirkin <> --- content.tex
25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/content.tex b/content.tex index e70473e..199fb1e 100644 --- a/content.tex +++ b/content.tex @@ -1115,6 +1115,31 @@ For all queues, the value cap.length presented by the device MUST satisty: The device MUST present at least one VIRTIO_PCI_CAP_ISR_CFG capability. This refers to at least a single byte, which contains the 8-bit ISR status field.
+subsection{ISR status field}label{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / ISR status field} + +ISR status field is used for INT#x interrupt handling. +Driver MUST NOT access ISR field when MSI-X capability +is enabled. + +egin{tabular}{ l l l } +hline +Bits
& 0
& 1
& 2 to 31 \ +hline +Purpose
& Device Configuration Interrupt & Queue Interrupt & Reserved \ +hline +end{tabular} + +If MSI-X capability is disabled, device MUST set Interrupt Status +bit in the PCI Status register in the PCI Configuration Header of +the device to the logical OR of all bits in ISR status field of +the device. Device then asserts/deasserts INT#x interrupts unless masked +according to standard PCI rules hyperref[intro:PCI]{[PCI]}. + +Device MUST reset the ISR status field to 0 on read. + +In this way, driver read of ISR status causes the device to de-assert +an interrupt. + subsubsection{Device specific structure}label{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / Device specific structure}
The device MAY present at least one VIRTIO_PCI_CAP_DEVICE_CFG capability (some
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MST
