xproc specification - implicit and explicit input/output ports?

Hi,

Obviously the specification/implementation of the ports is a point to
discuss.

I assume for the majority of the pipeline use cases the position of
steps (and constructs) implies the chaining of input and output ports in
the sequence of its appearance. That in mind it would be the easiest way
to omit the explicit port entries where the intention of chaining the
input and output ports is expressed by position of the components. Going
this way it is necessary to write port entries only for the situation in
which one want deviate the ordinary sequence.

Any response is much appreciated.

Best Regard

Joerg Moebius