[PATCH 10/10] PCI: explicitly document ISR status field

["Michael S. Tsirkin" <mst@redhat.com>]

Feedback on ISR status register:
	It would be helpful if this section provided the meaning of each
	bit in the register.

ISR use is scattered all around the place.
Add a section describing the format and semantics.

Cc: Arun Subbarao <asubbarao@lnxw.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 content.tex | 24 +++++++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/content.tex b/content.tex
index 1ae41e2..c00a1a9 100644
--- a/content.tex
+++ b/content.tex
@@ -1117,15 +1117,33 @@ For all queues, the value \field{cap.length} presented by the device MUST satist
 \subsubsection{ISR status capability}\label{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / ISR status capability}
 
 The device MUST present at least one VIRTIO_PCI_CAP_ISR_CFG capability.  This
-refers to at least a single byte, which contains the 8-bit ISR status field:
+refers to at least a single byte, which contains the 8-bit ISR status field.
+
+The \field{offset} for the ISR status has no specific alignment requirements.
+
+\subsection{ISR status field}\label{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / ISR status field}
+
+\field{ISR status} is used for INT#x interrupt handling.
+Driver MUST NOT access \field{ISR status} when MSI-X capability
+is enabled.
+
 \begin{lstlisting}
 #define VIRTIO_PCI_ISR_VQ       0x1
 #define VIRTIO_PCI_ISR_CONFIG   0x2
 \end{lstlisting}
 
-See sections \ref{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI-specific Initialization And Device Operation / Virtqueue Interrupts From The Device} and \ref{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI-specific Initialization And Device Operation / Notification of Device Configuration Changes} for how this is used.
+If MSI-X capability is disabled, device MUST set Interrupt Status
+bit in the PCI Status register in the PCI Configuration Header of
+the device to the logical OR of all bits in \field{ISR status} of
+the device.  Device then asserts/deasserts INT#x interrupts unless masked
+according to standard PCI rules \hyperref[intro:PCI]{[PCI]}.
 
-The \field{offset} for the ISR status has no specific alignment requirements.
+Device MUST reset \field{ISR status} to 0 on read.
+
+In this way, driver read of \field{ISR status} can causes the device to de-assert
+an interrupt.
+
+See sections \ref{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI-specific Initialization And Device Operation / Virtqueue Interrupts From The Device} and \ref{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI-specific Initialization And Device Operation / Notification of Device Configuration Changes} for how this is used.
 
 \subsubsection{Device specific structure}\label{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / Device specific structure}
 
-- 
MST